The present invention relates to arithmetic processing techniques, and more particularly to an arithmetic processing method and apparatus suitable for performing a arithmetic or logical operation through a minimum number of operation cycles, such as in the case of executing a vector sum instruction wherein intermediate operation results during operation are used as input data to thus repeat similar operations and obtain a final result.
A known conventional arithmetic processing system for performing a vector sum operation or the like is disclosed, e.g., in the publication JP-A-59-47643 by the present assignee, and in other publications.
According to this system, in performing an arithmetic operation for a vector sum S of, e.g., L vector data, i.e., vector elements V.sub.1, V.sub.2, . . . , V.sub.L, wherein EQU S=V.sub.1 +V.sub.2 +. . .+V.sub.L
the operation can be processed at high speed by changing the number of post-process operation cycles in accordance with the number L of operation data on the condition that the operation data number L is less than the operation stage number.
With the above-described conventional arithmetic processing system, the number of post-process operation cycles can be changed in accordance with the number of operation data, and if the operation data number is less than the operation stage number, the number of post-process operation cycles can be reduced to accordingly reduce a total number of operation cycles. However, such a system does not pay attention to the control of operation stages before the post-process cycles, thus posing a problem that the total number of operation cycles inclusive of the post-process cycles cannot be minimized.